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gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: june 2004 document no. 522 - 26 - 03 data sheet gs1522 features ? smpte 292m compliant 20:1 parallel to serial conversion nrz(i) encoder & smpte scrambler with selectable bypass nrz to nrz(i) seri al data conversion 1.485gb/s and 1.48 5/1.001gb/s operation lock detect output selectable dual or quad 75 ? cable driver outputs 8 bit or 10 bit input data support 20 bit wide inputs pb-free and green 3.3v and 5v cmos/ttl compatible inputs single +5.0v power supply applications smpte 292m serial digital interfaces for video cameras, camcorders, vtrs, signal generators, portable equip- ment, and nles. description the gs1522 is a monolithic bipolar integrated circuit designed to serialize smpte 274m and smpte 260m bit parallel digital signals. this device performs the following functions: ? sync word mapping for 8-bit/10-bit operation. parallel to serial conversion of luma & chroma data interleaving of luma and chroma data data scrambling (using the x 9 +x 4 +1 algorithm) conversion of nrz to nrzi se rial data (using the (x+1) algorithm) selectable dual or quad 75 ? cable driver outputs lock detect output 1.485gb/s or 1.485 /1.001gb/s operation this device requires a single 5v supply and typically consumes less than 1000mw of power while driving two 75 ? cables. the gs1522 uses the go1515 external vco connected to the internal pll circuitry to achieve ultra low noise pll performance. functional block diagram ordering information part number package temperature pb-free and green gs1522-cqr 128 pin mqfp 0c to 70c no GS1522-CQRE3 128 pin mqfp 0c to 70c yes sync detect smpte scrambler interleaver parallel to serial converter nrz to nrzi pll input latch go1515 o/p0 o/p1 pll_lock sdo1_en r set1 sdo1 sdo0 r set0 bypass reset sync_detect _disable pclk_in data_in[19:0] reset bypass s clk p load mute 20 20 sdo0 sdo1 hd-linx ? gs1522 hdtv serial digital serializer
gennum corporation 522 - 26 - 03 2 of 20 gs1522 absolute maximum ratings parameter value supply voltage (v s )5.5v input voltage range (any input) v ee ? 0.5 < v in < v cc + 0.5 dc input current (any input) tbd power dissipation (v cc = 5.25v) tbd input esd voltage tbd die temperature 125c operating temperature range 0c t a 70c storage temperature range -40c t s 150c lead temperature (soldering 10 seconds) 260 c ac electrical characteristics v cc = 5v, v ee = 0v, t a = 0c to 70c unless otherwise specified. parameter conditions symbol min typ max units notes serial data bit rate smpte 292m br sdo - 1.485 - gb/s 1.485/1.001gb/s also digital serial data outputs differential outputs v sdo 750 800 850 mv p-p with 52.3 ? 1% r set resistor rise/fall times, 20-80% t r , t f - 150 270 ps overshoot - 0 7 % output return loss @ 1.485ghz orl 15 17 - db as per smpte292m (5mhz to clock frequency), using gennum evaluation board, recommended layout and components. lock time worst case t lock - 200 250 ms typical loop bandwidth 0.1db peaking, 1.485gb/s - 0.200 1.5 mhz intrinsic jitter pseudo-random prbs (2 23 -1) (200khz lbw) t ijr - - 100 ps p-p pathological prbs (2 23 -1) (200khz lbw) t ijp - - 100 ps p-p pseudo-random (1.5 mhz lbw) t ijr - - 100 ps p-p pathological (1.5 mhz lbw) t ijp - - 100 ps p-p
gennum corporation 522 - 26 - 03 3 of 20 gs1522 ac electrical characteristics - parallel to serial stage v dd = 5v, t a = 0c to 70c unless otherwise specified. parameter conditions symbol min typ max units notes input voltage levels v il - - 0.8 v for compatibility with ttl voltage levels v ih 2.0 - - v for compatibility with ttl voltage levels input capacitance c in -12pf output voltage levels v ol - - 0.4 v for compatibility with ttl voltage levels v oh 2.4 - - v for compatibility with ttl voltage levels parallel input clock frequency p clk_in - 74.25 - mhz 74.25/1.001mhz also input clock pulse width low t pwl 5--ns input clock pulse width high t pwh 5--ns input clock rise/fall time t r , t f - 500 1000 ps 20% to 80% input clock rise/fall time matching t rfm -200-ps input setup time t su 1.0 - - ns input hold time t ih 0--ns dc electrical characteristics v cc = 5v, v ee = 0v, t a = 0c to 70c unless otherwise specified. parameter conditions symbol min typ max units notes positive supply voltage operating range v cc 4.75 5.00 5.25 v power (system power) v cc = 5.00v, t=25c p d - 950 - mw (driving two 75 ? outputs) v cc = 5.00v, t=25c p d - 1170 - mw (driving four 75 ? outputs) supply current v cc = 5.25v, t=70c - - 300 ma (driving four 75 ? outputs) v cc = 5.00v, t=25c - 234 - ma (driving four 75 ? outputs) sdo1 disabled v cc = 5.25v, 70c - - 240 ma (driving two 75 ? outputs) sdo1 disabled v cc = 5.0v, 25c - 190 - ma (driving two 75 ? outputs)
gennum corporation 522 - 26 - 03 4 of 20 gs1522 pin connections nc nc nc nc nc nc nc sdo1_en v ee2 v ee2 v ee2 v ee2 v ee2 v cc2 v cc2 v cc2 v cc2 v cc2 nc nc v ee2 reset bypass pll_lock nc xdiv20 nc nc buf_v ee nc nc nc nc nc nc nc pclk_in v ee3 nc nc nc nc nc nc nc nc nc vco vco pd_v ee pdsub_v ee iji pd_v cc nc nc lfs nc lfs plcap dm plcap dft_v ee lfa_v ee lfa lbcont lfa_v cc nc v cc3 v ee3 sync_detect_disable nc nc nc nc nc nc osc_v ee a0 nc nc nc v ee2 r set0 v cc2 nc sdo0 sdo_nc sdo0 nc nc nc sdo1 sdo_nc sdo1 nc v cc2 r set1 nc nc nc nc nc data_in[19] data_in[18] data_in[17] data_in[16] data_in[15] nc nc data_in[14] data_in[13] data_in[12] data_in[11] data_in[10] data_in[9] nc nc data_in[8] data_in[7] nc nc data_in[6] data_in[5] data_in[4] data_in[3] data_in[2] data_in[1] data_in[0] 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 gs1522 top view note: no heat sink required
gennum corporation 522 - 26 - 03 5 of 20 gs1522 pin descriptions number symbol level type description 1, 95 v ee3 power input negative supply. most negative power supply connection, for input stage. 2 pclk_in ttl input parallel data clock . 74.25 or 74.25/1.001mhz 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 19, 20, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,46, 50, 51, 52, 56, 60, 61, 62, 65, 66, 67, 68, 69, 70, 71, 72, 73, 80, 81, 83, 93, 97, 98, 99, 100, 101, 102, 108, 109, 116, 117, 120, 121 nc no connect . these pins are not used internally. these pins should be floating. 10 buf_v ee power test negative supply/test pin . most negative power supply connection. for buffer for oscillator/divider for test purposes only. leave floating for normal operation. 13 xdiv20 ttl test te s t p i n . test block output. leave floating for normal operation. 15 pll_lock ttl output status signal output . indicates when the gs1522 is phase locked to the incoming pclk_in clock si gnal. logic high indicates pll is in lock. logic low indicates pll is out of lock. 16 bypass ttl input control signal input . used to bypass the scrambling function if data is already scrambled by gs1501 or if non-smpte encoded data stream such as 8b/10b is to be transmitted. when bypass is low, the smpte scrambler and nrz(i) encoder are enabled. when bypass is high, the smpte scrambler and nrz(i) encoder are bypassed. 17 reset ttl input control signal input . used to reset the smpte scrambler. for logic high; resets the smpte scrambler and nrz(i) encoder. for logic low: normal smpte scrambler and nrz(i) encoder operation. 18, 26, 27, 28, 29, 30, 59 v ee2 power input negative supply . most negative power supply connection. for cable driver outputs and all other digital circuitry excluding input stage and pll stage. 21, 22, 23, 24, 25, 45, 57 v cc2 power input positive supply . most positive power supply connection. for cable driver outputs and all other digita l circuitry excluding input stage and pll stage. 31 sdo1_en power input control signal input . used to enable or disable the second serial data output stage. this signal mu st be tied to gnd to enable this stage. do not connect to a logic low. 44 r set1 input control signal input . external resistor is used to set the data output amplitude for sdo1 and sdo1 . use a 1% resistor. 47, 49 sdo1 , sdo1 analog output serial data output signal . current mode serial data output #1. use 75 ? 1% pull up resistors to v cc2 . 48, 54 sdo_nc no connect . not used internally. this pin must be left floating. 53, 55 sdo0 , sdo0 analog output serial data output signal . current mode serial data output #0. use 75 ? 1% pull up resistors to v cc2 . 58 r set0 analog input control signal input . external resistor is used to set the data output amplitude for sdo0 and sdo0 . use a 1% resistor.
gennum corporation 522 - 26 - 03 6 of 20 gs1522 63 a0 ttl test test signal . used for manufacturing test purposes only. this pin must be tied low for normal operation. 64 osc_v ee power input negative supply . ground for ring oscillator. this pin must be floating for normal operation. 74 vco analog input control signal input . input pin is ac coupled to ground using a 50 ? transmission line. 75 vco analog input control signal input . voltage controlled oscillat or input. this pin is connected to the output pin of the go1515 vco. this pin must be connected to the go1515 vco output pin via a 50 ? transmission line. 76 pd_v ee power input negative supply . most negative power supply connection. for phase detector stage. 77 pdsub_v ee power input guard ring . ground guard ring connection to isolate phase detector in pll stage. 78 iji analog output status signal output . indicates the amount of excessive jitter on the incoming sdi and sdi input. 79 pd_v cc power input positive supply . most positive power supply connection. for phase detector stage. 82, 84 lfs, lfs analog input loop filter connections . 85, 87 plcap, plcap analog input control signal input . phase lock detect time constant capacitor. 86 dm test signal . used for manufacturing test only. this pin must be left floating in normal operation. 88 dft_v ee power input most negative power supply connection . enables the jitter demodulator functionality. this pin should be connected to ground. if left floating, the dm funct ion is disabled resulting in a current saving of 340a. 89 lfa_v ee power input negative supply . most negative power supply connection. for loop filter stage. 90 lfa analog output control signal output . control voltage for go1515 vco. 91 lbcont analog input control signal input . used to provide electronic control of loop bandwidth. 92 lfa_v cc power input positive supply . most positive power supply connection. for loop filter stage. 94 v cc3 power input positive supply . most positive power supply connection. for input stage. 96 sync_detect_disable ttl input control signal input . used to disable the sync detection function. logic high disables sync detection. logic low: 000-003 is mapped into 000 and 3fc-3ff is mapped into 3ff for 8-bit operation. 103, 104, 105, 106, 107, 110, 111, 112, 113, 114, 115, 118, 119, 122, 123, 124, 125, 126, 127, 128 data_in[19:0] ttl input input data bus . the device receives a 20 bits data stream running at 74.25 or 74.25/1.001 mhz from the gs1501 hdtv formatter or gs1511 hdtv formatter. input data can be in smpte292m scrambled or unscrambled format. data_in[19] is the msb (pin 103). data_in[0] is the lsb (pin 128). pin descriptions (continued) number symbol level type description
gennum corporation 522 - 26 - 03 7 of 20 gs1522 input/output circuits fig. 1 vco/vco input circuit fig. 2 dm output circuit fig. 3 plcap/plcap output circuit fig. 4 lfa circuit fig. 5 lfs output circuit fig. 6 lfs input circuit pd_v ee pd_v cc vco vco 50 10k 5k 5k 10k 31p dft_v ee 10k 10k dm 85a pd_v cc pd_v ee 20k 10k plcap plcap 100a pd_v cc lfa_v ee lfa_v cc 40 40 500 5ma 100a lfa lfa_v ee lfa_v cc 25k 400a lfs lfa_v ee lfa_v cc 100a 100a 100a 100a 10k 5k lfs
gennum corporation 522 - 26 - 03 8 of 20 gs1522 fig. 7 pll_lock output circuit fig. 8 iji output circuit fig. 9 sdo/sdo output circuit fig. 10 data input and sync_detect_disable circuit fig. 11 pclk_in circuit fig. 12 reset circuit pd_v ee pd_v cc all on-chip resistors have 20% tolerance at room temperature. 10k pll_lock pd_v cc iji 10k 5k v cc 30k a pd_v ee r set sdo sdo + - cd_v ee v cc3 2k v ee3 bias 10k d0 - d19, sync_detect_disable v cc 1k v ee bias 5k pclk_in v cc 20k v ee bias 10k reset
gennum corporation 522 - 26 - 03 9 of 20 gs1522 fig. 13 bypass circuit detailed description the gs1522 hdtv serializer is a bipolar integrated circuit used to convert parallel data into serial format according to the smpte 292m standard. the device encodes both 8-bit and 10-bit ttl compatible parallel signals producing a serial data rate of 1.485gb/s. the device operates from a single 5v supply and is available in a 128 pin mqfp package. the functional blocks within the device include the input latches, interleaver, sync detector, parallel to serial converter, smpte scrambler, nrz to nrz(i) converter, two internal cable drivers, pll for 20x parallel clock multiplication and lock detect circuitry. 1. input latches the 20-bit input latch accepts either 3.3v or 5v cmos/ttl inputs. the input data is buffered and then latched on the rising edge of the pclk_in pin (2). the output of the latch is a differential signal for increased noise immunity. further noise isolation is provided by the use of separate power supplies. 2. interleaver the interleaver takes the 20-bit wide parallel data (y and c) and reduces it internally to a 10-bit wide word by alternating the y and c data words according to smpte 292m, section 6.1. 3. sync detector the sync detector looks for the reserved words 000-003 and 3fc-3ff in 10-bit hexadecimal, or 00-03 and fc-ff in 8-bit hexadecimal used in the trs-id sync word. when there is an occurrence of all zeros or all ones in the eight higher order bits, the lower two bits are forced to zeros or ones respectively. this allows the system to be compatible with 8-bit and 10-bit data. for non-smpte standard parallel data, a logic input sync detect disable pin (96) is available to disable this feature. 4. scrambler the scrambler is a linear feedback shift register used to pseudo-randomize the incoming data according to the fixed polynomial (x 9 +x 4 +1). this minimizes the dc component in the output serial stream. the nrz to nrz(i) converter uses another polynomial (x+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. to disable these features, set the bypass pin (16) high. 5. slew phase lock loop (s-pll) an innovative feature of the gs1522 is the slew phase lock loop (s-pll). when a step phase change is applied to the pll, the output phase gains constant rate of change with respect to time. this behavior is termed slew. figure 14 shows an example of input an d output phase variation over time for slew and linear (conventional) plls. since the slewing is a non-linear behavior, the small signal analysis cannot be done in the same way as it is for the standard pll. however, it is still possible to plot input jitter transfer characteristics at a constant input jitter modulation. slew plls offer several advant ages such as excellent noise immunity. the loop corrects small input jitter modulation immediately because of the infinite bandwidth. therefore, the small signal noise of the vco is cancelled immediately. the gs1522 uses a very clean, external vco called the go1515 (refer to the go1515 data sheet for details) . another advantage is the bi-l evel digital phase detector which provides constant loop bandwidth that is predominantly independent of the data transition density. the loop bandwidth of a co nventional tri-stable charge v cc 5k v ee bias 10k bypass 5k
gennum corporation 522 - 26 - 03 10 of 20 gs1522 pump drops with reducing data transitions. during pathological signals, the da ta transition density reduces from 0.5 to 0.05 but the slew pll?s performance does not change significantly. because most of the pll circuitry is digital, it is very robust as digital systems are generally more robust than their analog counterparts. signals which represent the internal functionality, like dm (86), can be generated without adding additional artifacts. thus, system debugging is possible with these features. the complete slew pll is made up of several blocks including the phase detector, the charge pump and an external voltage controlled oscillator (vco) which are described in the following sections. phase lock loop frequency synthesis and lock logic are also described. fig. 14 pll characteristics 5.1. phase detector the phase detector portion of the slew pll used in the gs1522 is a bi-level digital phase detector. it indicates whether the data transition occurred before or after with respect to the falling edge of the internal clock. when the phase detector is locked, the data transition edges are aligned to the falling edge of the clock. the input data is then sampled by the rising edge of the clock, as shown in figure 15. in this manner, the allowed input jitter is 1ui p-p in an ideal situation. however, due to setup and hold time, the gs1522 typically achieves 0.8ui p-p input jitter tolerance without causing any errors in this block. when the signal is locked to the internal clock, the control output from the phase detector is refres hed at the transition of each rising edge of the data input. during this time, the phase of the clock drifts in one direction. fig. 15 phase detector characteristics during pathological signals, the amount of jitter that the phase detector will add can be calculated. by choosing the proper loop bandwidth, th e amount of phase detector induced jitter can also be limited. typically, for a 1.41mhz loop bandwidth at 0.2ui inpu t jitter modulation, the phase detector induced jitter is about 0.015uip-p. this is not significant, even in the presence of pathological signals. 5.2. charge pump the charge pump in a slew pll is different from the charge pump in a linear pll. there are two main functions of the charge pump: to hold the frequency information of the input data and to provide a binary control voltage to the vco. the charge pump holds the frequency information of the input data. this information is held by c cp1 which is connected between lfs (82) and lfs (84). c cp2 , which is connected between lfs and lfa_v ee (89), is used to remove common mode noise. both c cp1 and c cp2 should have the same value. the charge pump provides a binary control voltage to the vco depending upon the phas e detector output. the output pin lfa (90) controls the vco. internally there is a 500 ? pull-up resistor which is driven with a 100a current called p . another analog current f , with 5ma maximum drive proportional to the voltage across the c cp1 , is applied at the same node. the voltage at the lfa node is v lfa_vcc - 500( p + f ) at any time. because of the integrator, f changes very slowly whereas p can change at the positive ed ge of the data transition as often as a clock period. in the locked position, the average voltage at lfa (v lfa_vcc ? 500( p /2+ f ) is such that vco generates frequency ? equal to the data rate clock frequency. since p is changing all the time between 0a and 100a, there are two levels ge nerated at the lfa output. 5.3. vco the go1515 is an external hybrid vco which has a centre frequency of 1.485ghz. it is guaranteed to provide 1.485/1.001ghz within the control voltage (3.1v ? 4.65v) of the gs1522 over process, po wer supply and temperature. 0.2 0.1 0.0 input output slew pll response phase (ui) 0.2 0.1 0.0 input output linear (conventional) pll response phase (ui) in-phase clock input clock with jitter output data 0.8ui re-timing edge phase alignment edge
gennum corporation 522 - 26 - 03 11 of 20 gs1522 the go1515 is a very clean frequency source and, because of the internal high q resonator, is an order of magnitude more immune to external noise as compared to on-chip vcos. the vco gain, k?, is nominally 16mhz/v. the control voltage around the averag e lfa voltage is 500 x p /2. this produces two frequencies off from the centre by ? = k? x 500 x p /2. 5.4. phase lock loop frequency synthesis the gs1522 requires the hdtv parallel clock (74.25 or 74.25/1.001mhz) to synthesize a serial clock which is 20 times the parallel clock frequency (1.485mhz) using a phase locked loop (pll). this serial clock is then used to strobe the output serial data. figure 16 illustrates this operation. the vco is normally free-running at a frequency close to the serial data rate. a divide-by-20 circuit converts the free running serial clock frequency to approximately that of the parallel clock. within the phase detector, the divided- by-20 serial clock is then compared to the reference parallel clock from the pclk_in pin (2). based on the leading or lagging alignment of the divided clock to the input reference clock, the serial data output is synchronized to the incoming parallel clock. fig. 16 phase lock loop frequency synthesis 5.5. lock logic logic is used to produce the pll_lock (15) signal which is based on the lfs signal and phase lock signal. when there is no data input, the in tegrator charges and eventually saturates at either end. by sensing the satu ration of the integrator, it is determined that no data is present. if there is no data present or phase lock is low, the lock signal is made low. logic signals are used to acquire the frequency by sweeping the integrator. injecting a current into the summing node of the integrator achieves the sweep. the sweep is disabled when phase lock is asserted. the direction of the sweep is changed when lfs saturates at either end. 6. lbcont the lbcont pin (91) is used to adjust the loop bandwidth by externally changing the internal charge pump current. for maximum loop bandwidth , connect lbcont to the most positive power supply. for medium loop bandwidth, connect lbcont through a pull-up resistor (r pull-up ). for low loop bandwidth, leave lbcont floating. the formula below shows the change in the loop bandwidth using r pull-up. where lbw nominal is the loop bandwidth when lbcont is left floating. 7. loop bandwidth optimization since the feed back loop has only digital circuits, the small signal analysis does not appl y to the system. the effective loop bandwidth scales with the amount of input jitter modulation index. the follo wing table summarizes the relationship between input jitter modulation index and bandwidth when r cp1 and c cp3 are not used. see the typical application circuit for the location of r cp1 and c cp3 . the product of the input jitter modulation (ijm) and the bandwidth (bw) is a constant. in this case, it is 282.9khzui. the loop bandwidth automatically reduces with increasing input jitter, which results in the cleanest signal possible. using a series combination of r cp1 and c cp3 in parallel to an on-chip resistor ( see the typical application circuit ) can reduce the loop bandwidth of the gs1522. the parallel combination of the resistors is directly proportional to the bandwidth factor. for example, the on-chip 500 ? resistor yields 282.9khzui. if a 50 ? resistor is connected in parallel, the effective resistance will be (50:500) 45.45 ? . this resistance yields a bandwidth factor of [282.9 x (45.45/500)] = 25.72khzui the capacitance c cp3 in series with the r cp1 should be chosen such that the rc factor is 50f. for example, r cp1 =50 ? requires c cp3 =1f. pclk_in phase detector divide-by-20 go1515 vco gs1522 pll table 1: relationship between input jitter modulation index and bandwidth input jitter modulation index bandwidth bw jitter factor (jitter modulation x bw) 0.05 5.657mhz 282.9khzui 0.10 2.828mhz 282.9khzui 0.20 1.414mhz 282.9khzui 0.50 565.7khz 282.9khzui lbw lbw nominal 25k ? r pull up ? + () 5k ? r pull up ? + () ----------------------------------------------------- - =
gennum corporation 522 - 26 - 03 12 of 20 gs1522 the synchronous lock time increases with reduced bandwidth. nominal synchronous lock time is equal to [ /bandwidth factor]. that is, the default bandwidth factor (282.9khzui) yields 1.25s. for 25.72khzui, the synchronous lock time is 0.3535/25.72k = 13.75s. since the c cp1 , c cp2 and c cp3 are also charged, it is measured to be about 11s which is slightly less than the calcul ated value of 13.75s. the k? of the vco (go1515) is specified with a minimum of 11mhz/v and maximum of 21mhz/v which is about 32% variation. the 500 x p /2 varies about 10%. the resulting bandwidth factor varies by approximately 45% when no r cp1 and c cp3 are used. p by itself may vary by 30% so the variability for lower bandwidths increases by an additional 30%. the c cp1 and c cp2 capacitors should be changed with reduced bandwidths. smaller c cp1 and c cp2 capacitors result in jitter peaking, lower stability, less probability of locking but at the same time lowering the asynchronous lock time. therefore, there is a trade-off between asynchronous lock time and jitter peaking/stability. these capacitors should be as large as possible for the allowable lock time and should be no smaller than the allowed value. with the recommended values, jitter peaking of less than 0.1db has been measur ed at the lower loop bandwidth as shown in figure 17. at higher loop bandwidths, it is difficult to measure jitter peaking because of the limitation of the measurement unit. fig. 17 typical jitter peaking however, because relatively larger c cp1 and c cp2 capacitors can be used, over-d amping of the loop response occurs. an accurate jitter pe aking measurement of 0.1db for the gs1522 requires the modulation source to have a constant amount of jitter modulation index (within 0.1db or 1.2%) over the frequency range beyond the loop bandwidth. it has been determined that for 282.9khzui, the minimum value of the c cp1 and c cp2 capacitors should be no less than 0.5f. for added margin, 1f capacitors are recommended. the 1f value gives a lock time of about 60ms in one attempt. for 25.72khzui, these capacitors should be no less than 5.6f. this results in 340ms of lock time. if necessary, extra margin can be built by increasing these capacitors at the expense of a longer asynchronous lock time. bandwidths lower than 129khz at 0.2ui modulation have not been characterized, but it is believed that the bandwidth could be further lowered ( contact gennum?s video products applications for further details ). since a lower bandwidth has less correction for noise, extra care should be taken to minimize board noise. figures 18 and 19 show the two measured loop bandwidths at these two settings. table 2 summarizes the two bandwidth settings. fig. 18 typical jitter transfer curve at setting a in table 2 fig. 19 typical jitter transfer curve at setting b in table 2 0.25 2
gennum corporation 522 - 26 - 03 13 of 20 gs1522 8. phase lock the phase lock circuit is used to determine the phase locked condition. it is done by generating a quadrature clock by delaying the in-phas e clock by 166ps (0.25ui at 1.5ghz) with the tolerance of 0.05ui. the in-phase clock is the clock whose falling edge is aligned to the data transition. when the pll is locked , the falling edge of the in- phase clock is aligned with the data edges as shown in figure 20. the quadrature cloc k is in a logic high state in the vicinity of input data transitions. the quadrature clock is sampled and latched by positive edges of the data transitions. the generated signal is low pass filtered with an rc network. the r is an on-chip 6.67k ? resistor and c pl is an internal capacitor (31pf). the time constant is about 200ns. fig. 20 pll circuit principles if the signal is not locked, the data transition phase could be anywhere with respect to the internal clock or the quadrature clock. in this case, the normalized filtered sample of the quadrature clock is 0.5. when vco is locked to the incoming data, data will only sample the quadrature clock when it is logic high. the normalized filtered sample quadrature clock is 1.0. we chose a threshold of 0.66 to generate the phase lock sig nal. because the threshold is lower than 1, it allows jitter to be greater than 0.5ui before the phase lock circuit reads it as ?not phase locked?. 9. input jitter indicator (iji) this signal indicates the amoun t of excessive jitter which occurs beyond the quadrature clock window (greater than 0.5ui, see figure 19 ). all the input data transitions occurring outside the quadrature clock window are captured and filtered by the low pass filter as mentioned in section 8, phase lock. the running time average of the ratio of the transitions insi de the quadrature clock and outside the quadrature is av ailable at the plcap/plcap pins (87 and 85). iji, which is the buffered signal available at the plcap, is provided so that loading does not effect the filter circuit. the signal at iji is referenced with the power supply such that the factor v iji /v cc is a constant over process and power supply for a given input jitter modulation. the iji signal has 10k ? output impedance. figure 21 shows the relationship of the iji signal with respect to the sine wave modulated input jitter. table 2: loop bandwidth setting options rcp1 ccp3 ccp1 ccp2 bw factor bw at 0.2 ui jitter modulation index asynchronous synchronous a open open 1.0 1.0 282.9khz 1.41mhz 60ms 1.25s b 50 1.0 5.6 5.6 25.72khz 129khz 340ms 11.0s in-phase clock input clock with jitter 0.8ui re-timing edge phase alignment edge quaderature clock plcap signal plcap signal 0.25ui table 3: iji voltage as a function of sinusoidal jitter p-p sine wave jitter in ui iji voltage 0.00 4.75 0.15 4.75 0.30 4.75 0.39 4.70 0.45 4.60 0.48 4.50 0.52 4.40 0.55 4.30 0.58 4.20 0.60 4.10 0.63 3.95
gennum corporation 522 - 26 - 03 14 of 20 gs1522 fig. 21 input jitter indicator (typical at t a = 25c) 10. jitter demodulation (dm) the differential jitter demodulation (dm) signal is available at the dm pin (86). this signal is the phase correction signal of the pll loop, which is ampl ified and buffered. if the input jitter is modulated, the pll trac ks the jitter if it is within loop bandwidth. to track the input jitter, the vco has to be adjusted by the phase detect or via the charge pump. thus, the signal which controls the vco contains the information of the input jitter modulation. the jitter demodulation signal is only valid if the input jitt er is less than 0.5uip-p. the dm signal has a 10k ? output impedance, which can be low pass filtered with appropriat e capacitors to eliminate high frequency noise. dft_v ee (88) should be connected to gnd to activate the dm signal. the dm signal can be used as a diagnostic tool. assume there is an hdtv sdi source which contains excessive noise during the horizontal blanking because of the transient current flowing in the power supply. to discover the source of the noise, probe around the source board with a low frequency oscilloscope (bandwidth < 20mhz) that is triggered with an appropriately filtered dm signal. the true cause of the modulation is synchronous and appears as a stationary signal with respect to the dm signal. figure 22 shows an example of such a situation. an hdtv sdi signal is modulated with a signal causing about 0.2ui jitter (channel 1). the gs1522 receives this signal and locks to it. figure 22 (channel 2) shows the dm signal. notice the wave shape of the dm signal, which is synchronous to the modulating signal. the dm signal can also be used to compare the output jitter of the hdtv signal source. fig. 22 jitter demodulation signal 11. mute the logic controls the mute block when the pll_lock (15) signal has a low logic state. when the mute signal is asserted, the previous state of the output is latched. 12. cable driver the outputs of the gs1522 are complementary current mode cable driver stages. the output swing and impedance can be varied. use table 4 to select the r set resistor for the desired output voltage level. linear interpolation can be used to determine the specific value of the resistor for a given output swing at the load impedance. for linear interpolation, use either figure 23 or the information in table 4. find the admittance and then, by inverting the admittance, a resistor value for the r set can be found. the output can be used as dual 0.8v 75 ? cable drivers. it can also be used as a differential transmission line driver. in this case, the pull-up resistor should match the impedance of the transmission line because the pull-up resistor acts as the source impedance. to reduce the swing and save power, use a higher value of r set resistor. there are hd-linx? products that can ha ndle such low input swings. note: for reliability, the minimum r set resistor cannot be less than 50 ? because of higher current density. iji signal (v) input jitter (ui) 0.00 0.20 0.40 0.60 0.80 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6
gennum corporation 522 - 26 - 03 15 of 20 gs1522 fig. 23 signal swing for various r set admittances when the outputs are used to differentially drive another device such as the gs1508, use 50 ? transmission lines with the smallest possible signal swing while allowing 10% variation at the output swing to select the correct r set resistor. to drive the gs1508, the recommended r set resistor is 150 ? . there is no need to compensate for the return-loss in this situation. the uncompensated waveform at the output is shown in figure 24. fig. 24 uncompensated output eye waveform fig. 25 compensated output eye waveform note: figures 24 and 25 show the waveforms on an oscilloscope using a 75 ? to 50 ? pad. source/end terminated output swing (v) 1/rset ( ? ) 0.00 0.01 0.02 0.03 1.0 0.8 0.6 0.4 0.2 0.0 75 ? 50 ? table 4: r set values for various output load conditions r set resistor admittance (g) of the r set resistor (= 1/r set resistor) output current transmission line, t e r m i n at e d at t h e end. (pull-up resistor at the source = 75 ? ) transmission line, t e r m i n at e d at t h e end. (pull-up resistor at the source = 50 ? ) 500.0 ? 0.0020 2.506ma 0.094v 0.063v 150.0 ? 0.0067 7.896ma 0.296v 0.197v 75.0 ? 0.0133 15.161ma 0.569v 0.379v 53.6 ? 0.0187 20.702ma 0.776v 0.517v 52.3 ? 0.0192 21.216ma 0.796v 0.530v 49.9 ? 0.0200 22.032ma 0.826v -
gennum corporation 522 - 26 - 03 16 of 20 gs1522 12. return loss in an application where the gs 1522 directly drives a cable, it is possible to achieve an output return loss (orl) of about 17db to 1.485ghz. pcb layout is very important. use the eb1522 as a reference layout ( see figures 28 to 31 ). when designing high frequency circuits, use very small ?0608? surface mount components with short distances between the components. to reduce pcb parasitic capacitance, provide openings in the ground plane. for best matching, a 12nh inductor in parallel with a 75 ? resistor and a 1.5pf capacitor matches the 75 ? cable impedance. the inductor and resistor cancel the parasitic capacitance while the capacitor cancels the inductive effect of the bond wire. to verify the performance of any layout, measure the return loss by shorting the inductor wi th a piece of wire without the gs1522 installed. unless the artwork is an exact copy of the recommended layout, verify every design for output return loss. tweak the layout until a return loss of 25db is attained while the gs1522 is not mounted and l1 is shorted. when the device is mounted, use different indu ctors to match the parasitic capacitance of the ic. when the correct inductor is used, maximum return loss of 5mhz to 800mhz is achievable. to increase the return loss 800mhz to 1.5ghz, use a shunt capacitor of 0.5pf to 1.5pf. the larger inductor causes slower rise/fall time. the larger shunt capacitor causes a kink in the output waveform . therefore, the waveform must be verified to meet sm pte 292m specifications. there are two levels at the output depending upon the output state (logic high or low). when taking measurements, latch the ou tputs in both states. an interpolation is necessary be cause the actual output node voltages are different when a stream of data is passing as compared to the static sit uation created when measuring return loss. see the gs1508 preliminary data sheet for more information . fig. 26 compensated output return loss at logic high fig. 27 compensated output return loss at logic low
gennum corporation 522 - 26 - 03 17 of 20 gs1522 typical application circuit v ee 3 pclk_in nc nc nc nc nc nc nc 1 2 3 4 5 6 7 8 9 buf_v ee nc nc xdiv20 nc pll_lock bypass reset v ee 2 nc nc v cc 2 v cc 2 v cc 2 v cc 2 v cc 2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 v ee 2 v ee 2 v ee 2 v ee 2 v ee 2 sdo1_en nc nc nc nc nc nc nc 26 27 28 29 30 31 32 33 34 35 36 37 38 65 66 67 68 69 70 72 73 74 75 76 77 78 79 80 81 82 83 84 nc nc nc nc nc nc nc nc vco pdsub_v ee iji pd_v cc nc nc nc pd_v ee lfs nc 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 dm plcap dft_v ee lfa_v ee lfa lbcont lfa_v cc nc v cc 3 v ee 3 sync_detect_disable nc nc nc nc nc nc 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nc nc nc nc nc r set1 v cc 2 nc sdo_nc sdo1 nc nc nc sdo_nc sdo0 nc v ee 2 nc v cc 2 r set0 nc nc a0 osc_v ee 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 123 122 124 125 126 127 128 data_in[19] data_in[18] data_in[17] data_in[16] data_in[15] nc nc data_in[14] data_in[13] data_in[12] data_in[11] data_in[10] nc nc data_in[8] data_in[7] nc nc data_in[6] data_in[5] data_in[4] data_in[3] data_in[2] data_in[1] data_in[0] note: l3 to l8 are 0 ? resistors. use 12nh inductors in noisy environments. 71 all resistors in ohms, all capacitors in farads, unless otherwise shown. sdo0 sdo1 data_in[9] plcap lfs vco d1_19 d1_18 d1_17 d1_16 d1_15 d1_14 d1_13 d1_12 d1_11 d1_10 d1_9 d1_6 d1_8 d1_7 d1_5 d1_4 d1_3 d1_2 d1_1 d1_0 v cc r2 75 r3 75 c8 10n c7 1p5 l1 12nh r4 75 r5 75 12nh 1p5 c11 47 47 + + c9 c10 l2 bnc_anchor j3 j1 j2 j4 second pair of bnc shown is for dual footprint option on input connectors v cc r set 52.3 v cc r6 0 pclk c21 optional pll_lock bypass reset c12 10n c16 470n v cc sync_detect_disable c5 10n lbcont lfa + + c1 10n 1 c cp2 c cp1 1 loop filter components v cc vco c4 10n c6 10n v cc v cc v cc c46 100n c47 10 l6 l7 c45 10 c48 100n v cc v cc c18 100n c19 10 l5 l8 c17 10 c20 100n v cc v cc c13 100n c40 10 l3 l4 c14 10 c15 100n v cc v cc r36 jmp r35 jmp iji lbcont note: r36 is an optional 0 ? resistor. leave floating. gs1522 bnc_anchor note: r35 is an optional 1k resistor. leave floating.
gennum corporation 522 - 26 - 03 18 of 20 gs1522 typical application circuit (continued) the figures above show the recommended application circuit for the gs1522. the external vco is the go1515 and is specifically designed to be used with the gs1522. figures 28 through 31 show an example pc board layout of the gs1522 ic and the go1515 vco. this application board layout does not reflect every detail of the typical application circuit. it is provided as a general guide to the location of the critical parts. fig. 28 top layer of eb1522 pcb layout fig. 29 ground layer of eb1522 pcb layout go1515 vco lfa c37 100n c38 10 1 2 3 v cc u2 go1515 4 5 6 7 + 8 vco gnd gnd v cc gnd vctr o/p gnd nc power connect v cc c41 + 10 c44 100n gs1522 lock detect r25 22k q1 led1 r22 150 v cc lock gs1522 reset circuit v cc gs1522 sync detect disable (10bit/8bit) hdr5 v cc hdr1 bypass v cc all resistors in ohms, all capacitors in farads, unless otherwise shown. + c cp3 sync_d etect_disable gs1522 scrambler bypass reset s1 12 34 r20 4k7 r cp1 50 1
gennum corporation 522 - 26 - 03 19 of 20 gs1522 fig. 30 power layer of eb1522 pcb layout fig. 31 bottom layer of eb1522 pcb layout application information please refer to the ebhdtx documentation for more detailed application and circuit information on using the gs1522 with the gs1501 and gs1511 formatters.
522 - 26 - 03 20 of 20 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation shinjuku green tower building 27f 6-14-1, nishi shinjuku shinjuku-ku, tokyo 160-0023 japan tel: +81 (03) 3349-5501 fax: +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ? copyright may 2000 gennum corporation. all rights reserved. printed in canada. gs1522 package dimensions 23.20 0.25 20.0 0.10 18.50 ref 17.20 0.25 14.0 0.10 12.50 ref 3.00 max 2.80 0.25 1.6 ref 0.30 max radius 0.13 min. radius 0.88 0.15 0.75 min 12 typ 0 - 7 0 -7 0.27 0.08 0.50 bsc 128 pin mqfp all dimensions are in millimetres. caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation revision notes: added pb-free and green information. for latest product information, visit www.gennum.com document identification data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.

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